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Our Digital Logic IP cores target applications within the wireless communication, networking and image processing technologies. These cores are made highly configurable, modular and technology independent so they are reusable and suitable for implementation into different FPGA and ASIC architectures. our cores are offered as either soft cores, meaning a VHDL or Verilog representation, or firm cores, meaning an EDIF netlist targeted to a particular technology. Some of the cores can also delivered as virtual application specified standard products (vASSPs) representing a complete solutions.

These cores are fully supported by test benches with both test vectors and expected results. Sample synthesis and place and route scripts are also provided as well as matlab models. We provide complete documentation along with specialist support by e-mail or phone in to the engineers if needed.

Wireless Communications (Click on the name to see further details or ask for a detailed data sheet)
	The IP core is the Digital Base Band part of the physical layer (PHY) for wireless networks conforming to the ECMA-368 standard Main Features : • Supports data rates of 53.3, 55, 80, 106.67, 110, 160, 200, 320, & 480 Mb/s • Conforms to ECMA-368 High Rate Ultra Wideband PHY and MAC Standard • Suitable for FPGA and ASIC Implementations. • Low complexity inner receiver based on a novel sign bit correlation method.
		A Time and Frequency Offset estimator for Multi-user OFDM, based on a method for the joint estimation of timing and carrier-frequency offset in Orthogonal frequency-division multiplexing (OFDM) systems.
			A Viterbi decoder core with built-in convolutional encoder, puncturer and depuncturer configurable at compile time to separately include or exclude a convolutional encoder, puncturer, decoder and depuncturer.Puncturer and depuncturer are configurable on the fly to support the coding rates of R = 1/3, 1/2, 5/8, 32/33 and 3/4.
			Highly configurable and modular Reed Solomon decoder and encoder core. Uses Hard decision decoding scheme and high speed decoding algorithm. The core is Configurable with respect to symbol size from 3 to 12 bits and any primitive field polynomial for a given symbol width. It supports code block length variable up to 4095 symbols
			A channel equalizer for OFDM Wireless LAN systems compliant with HIPERLAN/2 and IEEE 802.11a standard. Based on low complexity channel estimation and phase tracking algorithms for efficient implementation in FPGAs and ASICs
			NFC Digital Transceiver (coming soon)
			High-throughput Low Density Parity Check Decoder for DVB-S2 (coming soon)
Networking (Click on the name to see further details or ask for a detailed data sheet)
			The SPI-4.2 IP core implements and is fully compliant with the OIF-SPI4-02.1 System Packet Interface Phase 2 standard. This fully verified solution interconnects physical-layer devices to link-layer devices in 10 Gbps POS, ATM and Ethernet applications. Optimized for all Virtex™-5 and Virtex-4 devices, the core leverages SelectIO™ features to achieve both smaller and faster SPI-4.2 products; enabling higher-level functions such as switches, bridges, and NPU interfaces. An implementation of this core may assume any of the following connection forms: • Chip-to-Chip interface implemented with traces on a printed circuit board • A motherboard to daughterboard interface between 2 printed circuit boards • An interface between 2 printed circuit assemblies that are attached with a length of cable and appropriate connector

Main Features :

• Supports data rates of 53.3, 55, 80, 106.67, 110, 160, 200, 320, & 480 Mb/s • Conforms to ECMA-368 High Rate Ultra Wideband PHY and MAC Standard • Suitable for FPGA and ASIC Implementations. • Low complexity inner receiver based on a novel sign bit correlation method.

• Supports data rates of 53.3, 55, 80, 106.67, 110, 160, 200, 320, & 480 Mb/s
• Conforms to ECMA-368 High Rate Ultra Wideband PHY and MAC Standard
• Suitable for FPGA and ASIC Implementations.
• Low complexity inner receiver based on a novel sign bit correlation method.